1. Field of the Invention
Embodiments of the present invention relate to semiconductor memory devices, and more particularly, to a layout structure of bit line sense amplifiers of a semiconductor memory device.
2. Description of the Related Art
In general, in a semiconductor memory device, when a row address is input, a row decoder of a block selected by the row address is activated to enable a word line. A memory cell coupled to the enabled word line is turned on, in order to transmit data to a bit line.
Subsequently, data provided to the bit line is sensed by a bit line sense amplifier, and is transferred to a local input/output line or local data bus (hereinafter, referred to as ‘local input/output line’) via use of a column selection switch. The data transferred to the local input/output line is transmitted to a global input/output line and is output through an output buffer.
Typically, a semiconductor memory device includes a plurality of bit line sense amplifiers, a plurality of main bit lines, a plurality of sub bit lines, a plurality of column selection switches, a plurality of main local input/output lines, and a plurality of sub local input/output lines. Portions of the bit line sense amplifiers are typically adjacent to one another and share an active region. Sharing an active region may affect performance of the semiconductor memory device. A need, therefore, exists for a semiconductor memory device that addresses one or more limitations of the conventional art.